Successive approximation analogue to digital converters (ADCs) are one form of ADC that essentially performs a binary search across a range of signal values in order to match an input signal as closely as possible. Such ADCs are used in many electronic devices. One particular example where successive approximation ADCs are used to good effect is in sensors such as gyros and accelerometers, e.g. MEMS (micro electro-mechanical sensor) devices.
A MEMS accelerometer consists of a capacitive structure with interdigitated fingers connecting to suitable drive and pickoff electronics. Such devices can use either an open loop or a closed loop configuration. In open loop accelerometers the electronics are arranged to drive fixed electrodes with a sine or square wave signal and a proof mass moves under acceleration to provide a pickoff signal that is proportional to applied acceleration. WO 2004/076340 provides an example of an open loop accelerometer.
A similar or identical sensing structure can be used for closed loop operation by using drive electronics to provide a variable electrostatic force to the electrodes to provide force rebalancing. WO 2005/084351 provides an example of a closed loop electronic control circuit using pulse width modulation (PWM) of the drive signals.
In both the open loop configuration and the closed loop configuration it can be advantageous to convert the analogue pickoff output signal into the digital domain using an analogue to digital converter (ADC). In the open loop configuration this provides a digital signal that is proportional to acceleration and which can be used directly by the host system. In the closed loop configuration the conversion provides a digital signal that is proportional to the offset of the proof mass from the force rebalance null position, which can then be used with digital filtering to provide the required levels of drive electrostatic forces.
In both the open loop and the closed loop configuration it is desirable to have a high level of resolution and therefore a higher number of bits within the analogue to digital converter. In the open loop configuration the higher resolution allows the digital representation of the applied acceleration to be more accurate. In the closed loop configuration it allows the offset of the proof mass from the null position to be more accurately measured. The higher number of bits of the ADC is particularly beneficial where the dynamic range of the accelerometer is required to be large but it is still required to measure or control to a high degree of accuracy, e.g. down to below 100th of a g. For example if the required full scale operating range for the accelerometer is ±100 g, an ADC with only 10 bits will have a resolution of 0.2 g whereas an ADC with 14 bits will have a resolution of 0.012 g.
High ADC resolution is especially useful in systems when the random noise within the system is substantially smaller than the resolution of the ADC as the resolution will then directly influence the smallest signal that can be detected. This can be a problem for high dynamic range systems and can be partially solved by using a closed loop configuration to reduce the dynamic range required by the ADC. This however only works effectively providing the system is substantially linear (MEMS accelerometers are typically very nonlinear) and still requires ADC resolutions to be compatible with the resolution of the PWM system.
Monotonic behaviour is important for control systems. This means that an increase on the input should result in an increase on the output and a decrease on the input should result in a decrease on the output. In ADCs this means the avoidance of fluctuations on the output. In closed loop operation such non-monotonic fluctuations would reduce or destroy the stability of the feedback loop.
Achieving high resolution ADC converters with monotonic behaviour within an application specific integrated circuit (ASIC), which allows a fully integrated MEMS sensor to be achieved, is very difficult beyond 12 bits using standard techniques such as successive approximation (SAR) conversion. One option to achieve greater than 12 bits is to use a significant amount of trimming on each device. This is a calibration step that is performed after fabrication, whereby the individual on-chip elements of the converter are measured and adjusted so as to ensure the required monotonic operation. Trimming can be done mechanically, e.g. laser trimming can burn away small portions of resistors, or the trimming can be done electronically, e.g. by sub-dividing components and switching parts in and out of use during the trimming process to refine the final value. However these techniques add both significant area to the ASIC and cost through test time.
Another alternative for achieving higher resolution ADCs is to use sigma delta architecture ADCs. Sigma delta ADCs are normally single bit converters, although they may sometimes be multi-bit up to 3 or 4 bit. Sigma delta ADCs require significant over sampling with back end filtering to achieve high resolution converters. This requires a very high clock rate to allow the high oversampling. This in turn requires very careful design and layout to ensure that timing constraints are met. Also, a high order filter is required to convert the bit stream into the final digital value, adding latency to the signal path. High latency in the signal path reduces the loop bandwidth in a closed loop system, thus restricting the measurements. Low latency is desirable for use in dynamic systems where it is desired to measure accurately dynamic changes in the measured value, e.g. rapidly changing accelerations or gyro rates.